1. Field of the Invention
The present invention relates to a thin-film transistor (TFT) structure used in solid-state image sensors and liquid crystal displays and also to a method of fabricating such TFTs. Furthermore, the invention relates to MOS transistors used in an LSI and to a method of fabricating such MOS transistors.
2. Description of the Related Art
In recent years, commercial products whose performance has been improved by packing TFTs into large-sized devices have been put into the market. Also, commercial products which have been miniaturized by simplification of peripheral circuits have appeared on the market. Especially, small-sized personal computers which have started to be widespread since around 1990 and are known as notebook computers and laptop computers have large-sized liquid crystal displays. Of these large-sized liquid crystal displays, active matrix liquid crystal displays in which a TFT is disposed at each pixel have very excellent display performance. There is an urgent demand for reductions in costs of these active matrix liquid crystal displays.
Today, almost all manufactured TFTs used in these large-sized liquid crystal displays use amorphous silicon. However, amorphous TFTs exhibit lower performance compared with other transistors. For example, with respect to electron mobility, the electron mobility of an amorphous TFT is 10.sup.-4 to 10.sup.-3 times as high as the electron mobility of a single-crystal silicon transistor. Therefore, an IC forming a peripheral driver circuit for driving TFTs disposed at pixels is required to be disposed outside, the IC being made from single-crystal silicon.
Furthermore, in order to obtain a sufficiently high operating speed by supplying a sufficiently large current into TFTs disposed at pixels, it is necessary to set the channel width to a large value. This reduces the pixel aperture ratio which is one of factors capable of enhancing the display quality. In this way, these two parameters conflict with each other. Moreover, with respect to reliability, amorphous silicon film and amorphous silicon nitride film are electrically unstable intrinsically. Consequently, their long-term performance is not ensured.
A method of fabricating TFTs from polysilicon is expected to act as means for solving all of these disadvantages. In this method, ON currents which are higher than the ON currents of amorphous silicon TFTs by two or three orders of magnitude are obtained. Additionally, instability as encountered in amorphous silicon TFTs does not take place but rather excellent reliability is obtained. Moreover, both N-type and N-type transistors can be fabricated. Consequently, CMOS circuits can be built. It is easy to satisfy the present demand for lower electric power consumption.
Where TFTs are formed from this polysilicon, the peripheral driver circuit for driving TFTs disposed at pixels of an active matrix liquid crystal display can be made up of TFTs similar to the TFTs disposed at the pixels, because TFTs using a polysilicon thin film can have electrical characteristics and mobilities sufficient to construct the peripheral driver circuit.
Although the polysilicon TFTs have excellent properties in this way, their OFF current is high. Also, when a gate voltage is applied to the reverse bias side (in the case of an N-type TFT, the voltage is applied to the negative side; in the case of a P-type TFT, the voltage is applied to the positive side), the current is increased. In this manner, there remain numerous drawbacks to be solved. The OFF current referred to herein is the electrical current flowing between the source and drain at the point at which the TFT is driven into cutoff. For example, in the case of the N-channel type, this point is normally set to 0 V or more.
It is known that these problems (i.e., high OFF currents and increased current on the reverse bias side) can be circumvented by forming an offset structure or LDD (lightly doped drain) structure on the side of the drain electrode.
The offset structure is described in Japanese Patent Laid-Open No. 360580/1992 (hereinafter referred to as Reference 1). The LDD structure is described in Japanese Patent Publication No. 38755/1991 (hereinafter referred to as Reference 2), in "Submicron Device II", Electronic Material Series, 3rd print, published by Maruzen Publishing Company, Japan, Sep. 5, 1993, p. 187 (hereinafter referred to as Reference 3), and in "Ultrahigh-Speed MOS Devices", Ultrahigh-Speed Digital Device Series, Published by Baifukan Publishing Company, Japan, 1st print, Feb. 10, 1986, p. 151 (hereinafter referred to as Reference 4).
In these offset structure and LDD structure, the concentration of electric field between the drain region and the channel formation region is mitigated to lower the OFF current. Also, increase of current on the reverse side is suppressed.
Known methods of forming the LDD structure are described in References 3 and 4. In particular, after patterning gate electrodes, a silicon oxide film is formed by a film formation method which provides good step coverage. An etch-back step is performed by a highly anisotropic method. Side walls or spacers are formed beside the side surfaces of the gate electrodes. These side walls will act as a mask during doping.
In these methods, those portions which are located under the side walls or spacers are lightly doped with impurity ions to change these regions into field mitigation regions. In these methods, materials capable of withstanding high temperatures such as n.sup.+ polysilicon (n-type silicon having crystallites) and silicides are used to form gate electrodes, for the following reason. After completion of implantation of impurity ions for forming source/drain regions, a heat treatment is conducted above 500.degree. C. to anneal out damage to the active layer induced during the impurity ion implantation (generally, regions implanted with ions are made amorphous) and to activate the implanted impurity ions.
However, the polysilicon has a large internal stress and so where gate electrodes are formed from the polysilicon, the stress inside the gate electrodes is transmitted to the gate-insulating film and also to the channel formation region. Consequently, the electrical characteristics of the TFTs are affected. This causes the individual TFTs to have characteristics different from each other and induces instability, thus producing undesirable results.
On the other hand, gate electrodes are preferably made from a material having a low resistivity. Ever finer gate electrodes have been developed. Where miniaturization and larger scales of integration are taken into, consideration, it is required to use a material having the lowest sheet resistivity achievable. Gold, silver, copper, aluminum, and other materials are available as low-resistivity materials. However, gold and silver are expensive. Copper has the disadvantage that it diffuses during a heating step. Therefore, these metals are inappropriate. On the other hand, aluminum is cheap and has a small internal stress. Therefore, aluminum is a quite desirable material for forming gate electrodes.